Research Projects

No Student Title Selected References
1 Ashraf Al-Suyyagh GPU Computing: The Ascend of the Coprocessor
<Report>, <Presentation>
  1. S. Che, M. Boyer, J. Meng, D. Tarjan, JW. Sheafer, K. Skadron, “A Performance Study of General Purpose Applications on Graphics Processors using CUDA ”, Journal of Parallel and Distributed Computing, Volume 68, Issue 10, pp. 1370 – 1380, Elsevier, 2008
  2. O. Schenk, M. Christen, H. Burkhart “Algorithmic Performance Studies on Graphic Processing Units” Journal of Parallel and Distributed Computing, Volume 68, Issue 10, pp 1360-1369, Elsevier, 2008
  3. J. Nickolls, I. Buck, M. Garland, K. Skadron ,”Scalable Parallel Programming with CUDA”, ACM Queue, Vol 6, Issue 2, 2008 , pp 40-53
2 Yousef Yaseen Multi-core Processing: Advantages and Challenges
<Report>, <Presentation>
  1. Faxén, Karl-Filip, ed. and Bengtsson, Christer and Brorsson, Mats and Grahn, Håkan and Hagersten, Erik and Jonsson, Bengt and Kessler, Christoph and Lisper, Björn and Stenström, Per and Svensson, Bertil (2008) Multicore computing--the state of the art. Not published.
3 Asma Abdelkarim A Study on Cache Replacement Policies
<Report>, <Presentation>		 [4] Qureshi M., Jaleel A., Hasenplaugh W., Sebot J., Jr. S. & Emer J. (2008). Adaptive Insertion Policies for Managing Shared Caches. Proceedings of the 17th international conference on Parallel architectures and compilation techniques (PACt’08), pp. 208-219.
[6] Qureshi M., Jaleel A., Patt Y., Jr. S. & Emer J. (2007). Adaptive Insertion Policies for High Performance Caching. Proceedings of the 34th annual international symposium on Computer architecture (ISCA’07), pp. 381-391.
[10] Xie Y. & Loh G. (2009). PIPP: Promotion/Insertion Pseudo-Partitioning of Multi-Core Shared Caches. Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA’09), pp. 174-183.
4 Dua'a Al-Najdawi Trace Cashe
<Report>, <Presentation>		 1- Eric Rotenberg, James E. Smith, Steve Bennett, "Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching" micro, pp.24, 29th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'96), 1996.

2- MICHAEL BEHAR , AVI MENDELSON , AVINOAM KOLODNY, “Trace Cache Sampling Filter”.14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05) ,pp. 255-266 ,2005.

5- Bing Chen , Musawir Ali."Trace Cache", www.eecs.ucf.edu/~mali/TraceCache.doc - 2004-05-09.
5 Abeer Hyari A Comparative Study on Heterogeneous and Homogeneous Multiprocessors
<Report>, <Presentation>		 3- Heterogeneous and Homogeneous Multiprocessors" my main refernces: R. Kumar, D. Tullsen, N. Jouppi, R. Ranganathan. “Heterogeneous Chip Multiprocessors” Computer. Volume 38, Issue 11, pages 32-38, Nov. 2005.

7- S. Balakrishnan, R. Rajwar, M. Upton, K. Lai. “The Impact of Performance Asymmetry in Emerging Multicore Architectures”. Proc. Int’l Symp. Computer Architecture, IEEE CS Press, 2005, pp. 506-517.
6 Shereen Ismael Towards Precise Instruction Scheduling
<Report>, <Presentation>		 1- Gokhan Memik, Glenn Reinman, and William H. Mangione-Smith. Precise instruction Scheduling. Journal of Instruction-Level Parallelism 7 (2005) 1-29April.2005.

3- Memik, G., G. Reinman, and W. H. Mangione-Smith. Just Say No: Benefits of Early Cache Miss Determination. In International Symposium on High Performance Computer Architecture, Feb. 2003. Anaheim / CA.