University of Jordan

Computer Engineering Department

CPE 439: Computer Design Lab

Spring 2007

 

Instructors Dr. Gheith Abandah
Email abandah@ju.edu.jo
Home page http://www.abandah.com/gheith
Office Computer Engineering 405
Office hours
bulletMon 9:30-10:30
bulletTue 12:00 - 13:00
bulletThu 9:00 - 10:00
No. of credit hrs 1
Co-requisites CPE 432
Time and room Computer Design Lab
Textbook  
References

  1. Patterson and Hennessy. Computer Organization & Design: The Hardware/Software Interface, 2nd ed., Morgan Kaufmann, 1997.

  2. Hennessy and Patterson. Computer Architecture: A Quantitative Approach, 3rd ed., Morgan Kaufmann, 2002.

  3. S. Palnitkar, Verilog HDL, 2nd Ed., Prentice Hall, 2003.
Grading
Pre-Lab Reports and In-Lab Performance 20%
Post-Lab Reports 20%
Mid-Term Exam 20%
Final Exam 40%
Tentative outline

Using Verilog, the student designs and simulates the main parts of a computer: the ALU, registers, control unit, cache memory, system bus, and memory. At the end of the semester, the student integrates and simulates a complete computer design.
Handouts/Links:
bullet

PowerPoint presentation used in first session.

bulletD. Hyde, Handbook on Verilog HDL, pdf.
bulletLib439.v
bulletExperement I2: Introduction to Verilog - SR Latch
bulletExperiment 1: 32-Bit ALU
bulletExperiment 2: Three-Port Register File
bulletExperiment 3: Five-Stage Pipeline Datapath - Arithmetic and Memory Instructions
bulletExperiment 4: Five-Stage Pipeline Datapath - Adding Flow Control Instructions
bulletExperiment 5: Five-Stage Pipeline Datapath - Solving Data Hazards
bulletExperiment 6: Direct-Mapped Instruction Cache