 | Monday 12:00-13:00 |
| Wednesday 15:00-16:00 |
| Thursday 19:00-20:00 |
| Section 1: Monday 12:00-15:00, Logic and Computer Organization Lab |
| Section 2: Thursday 15:00-18:00, Logic and Computer Organization Lab |
| Section 3: Wednesday 15:00-18:00, Logic and Computer Organization Lab |
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Patterson and Hennessy. Computer Organization & Design: The Hardware/Software Interface, 2nd ed., Morgan Kaufmann, 1997.
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Hennessy and Patterson. Computer Architecture: A Quantitative Approach, 3rd ed., Morgan Kaufmann, 2002.
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S. Palnitkar, Verilog HDL, 2nd Ed., Prentice Hall, 2003.
Using Verilog, the student designs and simulates the main parts of a computer: the ALU, registers, control unit, cache memory, system bus, memory, and I/O devices. At the end of the semester, the student integrates and simulates a complete computer design.
| D. Hyde, Handbook on Verilog HDL, pdf. |
| Lib439.v |
| Experiment 1 |
| Experiment 2 |
| Experiment 3 |
| Experiment 4 |
| Experiment 5 |
| Experiment 6 |