University of Jordan |
Computer Engineering Department |
CPE 439 |
Computer Design Lab |
Fall 2005 |
Instructor | Dr. Gheith Abandah | |||||||||||||||||
abandah@ju.edu.jo | ||||||||||||||||||
Home page | http://www.abandah.com/gheith | |||||||||||||||||
Office | Computer Engineering 405 | |||||||||||||||||
Office hours | ||||||||||||||||||
No. of credit hrs | 1 | |||||||||||||||||
Co-requisites | CPE 432 | |||||||||||||||||
Time and room | Computer Design Lab | |||||||||||||||||
Textbook | ||||||||||||||||||
References |
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Grading | ||||||||||||||||||
Pre-Lab Reports and In-Lab Performance | 20% | |||||||||||||||||
Post-Lab Reports | 20% | |||||||||||||||||
Mid-Term Exam | 20% | |||||||||||||||||
Final Exam | 40% | |||||||||||||||||
Tentative outline |
Using Verilog, the student designs and simulates the main parts of a computer: the ALU, registers, control unit, cache memory, system bus, memory, and I/O devices. At the end of the semester, the student integrates and simulates a complete computer design. |
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Handouts/Links: |
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