University of Jordan

Computer Engineering Department

CPE 432: Computer Design

Spring 2009

 

Instructor Dr. Gheith Abandah
Email abandah@ju.edu.jo
Home page http://www.abandah.com/gheith
Office Computer Engineering 405
Office hours
bulletSun 9:00 - 10:00
bulletMon 2:00 - 3:00
bulletTue 9:00 - 10:00
No. of credit hrs 3
Prerequisites CPE 335: Computer Organization
Time and room
bulletSection 1: Sun, Tue, and Thu 8:00-9:00, CE 002
Textbook Hennessy and Patterson. Computer Architecture: A Quantitative Approach, 4th ed., Morgan Kaufmann, 2007.
References

  1. Patterson and Hennessy. Computer Organization & Design: The Hardware/Software Interface, 3rd ed., Morgan Kaufmann, 2005.

  2. D. Culler and J.P. Singh with A. Gupta. Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann, 1998.

  3. J. Hayes. Computer Architecture and Organization, 3rd ed., McGraw-Hill, 1998.
Grading
Mid-Term Exam 30%
3 Homeworks and 2 Quizzes: 3 Marks for each homework, and 11 marks for the 2 quizzes. 20%
Final Exam 50%
Policies
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Attendance is required.

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All submitted work must be yours.

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Cheating will not be tolerated.

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Homeworks are due on exam or quiz dates

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This course requires significant effort.
Tentative outline
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Introduction

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Instruction Set Principles

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Review of Pipelining

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Instruction-Level Parallelism and Its Exploitation

Midterm Exam

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Limits of Instruction-Level Parallelism

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Multiprocessors and Thread-Level Parallelism

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Memory Hierarchy Design

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Storage Systems

Final Exam

Special Dates
Sun 8 Feb 2009 Classes Begin
Sun 1 Mar 2009 Homework 1 Announcement
Sun 8 Mar 2009 Quiz 1 and Homework 1 Due
Sun 29 Mar 2009 Homework 2 Announcement
Sun 5 Apr 2009 Midterm Exam and Homework 2 Due (8:00-9:00)
Tue 28 Apr 2009 Homework 3 Announcement
Tue 5 May 2009 Quiz 2 and Homework 3 Due
Sun 24 May 2009 Last Lecture
Sun 31 May 2009 Final Exam (8:30-10:30)
Handouts

Slides

  1. Introduction and Technology Trends
  2. Quantitative Principles of Computer Design
  3. Instruction Set Principles
  4. Review of Pipelining
  5. Instruction Level Parallelism - Part I
  6. ILP II: Branch Prediction
  7. ILP III: Dynamic Scheduling
  8. ILP IV: Speculative Execution
  9. ILP V: Multiple Issue
  10. Limits to ILP
  11. Thread Level Parallelism, 11B. Multicore Processors
  12. Multiprocessor Introduction
  13. Snooping Cache Multiprocessors
  14. Directory-Based Multiprocessors
  15. Memory Hierarchy Review
  16. Advanced Memory Hierarchy
  17. Storage

Homeworks

  1. Homework 1 due Sun 8 Mar, 2009, Solution.
  2. Homework 2 due Sun 5 Apr, 2009, Solution.
  3. Homework 3 due Tue 5 May, 2009, Solution.

Quizzes and Exams

  1. Solutions of Quiz 1 given on Sun 8 Mar, 2009, Q1A, Q1B
  2. Midterm exam was given on Sunday 5 April, 2009, Solution
  3. Quiz 2 was given on Tue 5 May, 2009, Solution

Grades as of 23/5/2009 - Grades as entered in the electronic grades system (Page 1, Page 2)