 | Sunday 13:00-14:00 |
| Tuesday 10:00-11:00 |
| Section 1: Sun, Tue, and Thu 8:00-9:00, CPE 001 |
| Section 2: Sun, Tue, and Thu 9:00-10:00, EE 002 |
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Patterson and Hennessy. Computer Organization & Design: The Hardware/Software Interface, 2nd ed., Morgan Kaufmann, 1997.
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D. Culler and J.P. Singh with A. Gupta. Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann, 1998.
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J. Hayes. Computer Architecture and Organization, 3rd ed., McGraw-Hill, 1998.
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Introduction |
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Instruction Set Principles |
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Instruction-Level Parallelism and Its Dynamic Exploitation |
Mid-Term exam
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Exploiting Instruction-Level Parallelism with Software Approaches |
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Memory Hierarchy Design |
Second exam
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Multiprocessors and Thread-Level Parallelism |
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Storage Systems |
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Interconnection Networks and Clusters |
Final exam
HW1: Due 9/10/2005
Solve problems 1.3, 1.4, 1.9, and the following problem.
A program is executed on a 3-GHz processor. The program has the instruction counts shown in the table below. What is the CPU time?
| Instruction Type | Count | CPI |
| Memory | 1234 | 3 |
| Control | 2569 | 2 |
| ALU | 3912 | 1 |
Solution: Page 1, Page 2, Page 3 (problems not answered in these pages are answered in the textbook)
HW2: Due 20/10/2005
Solve problems 2.3, 2.4a, 2.6, 2.8, 2.11, 2.14, and 2.18
Solution: Page 1, Page 2, Page 3 (problems not answered in these pages are answered in the textbook)
HW3: Due 8/11/2005
A.1, A.2, A.3, A.4
Solution: Page 1, Page 2 (problems not answered in these pages are answered in the textbook)
HW4: 3.2, 3.3, 3.7, 3.14, 3.21
Solution: Page 1, Page 2 (problems not answered in these pages are answered in the textbook)
HW5: 4.1, 4.5, 4.7, 4.17, 4.20
Solutions are in the text book.
HW6: 5.1, 5.6, 5.16, 5.19
Solutions are in the text book.
Solution of Quiz 2 for Section 1
Solution of Quiz 2 for Section 2
*** Grades *** (Note: the student who did not write his name on the second exam's sheet in Section 2 should contact me)