University of Jordan |
Computer Engineering Department |
CPE 431: Performance Evaluation and Modeling |
Fall 2005 |
Instructor | Dr. Gheith Abandah | |||||||||||||
abandah@ju.edu.jo | ||||||||||||||
Home page | http://www.abandah.com/gheith | |||||||||||||
Office | Computer Engineering 405 | |||||||||||||
Office hours |
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No. of credit hrs | 3 | |||||||||||||
Prerequisites | CPE 232 | |||||||||||||
Time and room |
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Textbook | Raj Jain, The Art of Computer Systems Performance Analysis, Wiley, 1991. | |||||||||||||
References |
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Grading | ||||||||||||||
Assignments | 10% | |||||||||||||
Mid-Term Exam | 30% | |||||||||||||
Second Exam | 10% | |||||||||||||
Final Exam | 50% | |||||||||||||
Tentative outline |
Mid-Term exam
Second exam
Final exam |
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Handouts |
Assignment 1 Due 26/10/2005 Assignment 2 Due 7/11/2005 Assignment 3 (Due December 21, 2005) A good reference for Verilog is Hyde's Handbook on Verilog HDL VeriLogger Pro from SynaptiCAD is a good Verilog simulation environment. Use the following library in your Verilog simulations: lib431.v Assignment 4 (Due December 28, 2005) Assignment 5 (Due January 4, 2006) Assignment5.zip |