University of Jordan

Computer Engineering Department

CPE 231: Digital Logic

Fall 2008

 

Instructors Dr. Gheith Abandah, Dr. Ahmad Al-Sarhan, Eng. Tuqa Manasrah
Email abandah@ju.edu.jo, asarhan@hotmail.com, t.manasrah@ju.edu.jo
Homepage http://www.abandah.com/gheith/Courses/CPE231_F08
Office Computer Engineering 405  
Office Hours for Dr. Abandah
bulletSun 10:00 - 11:00
bulletMon and Wed 11:00 - 12:00
bulletThu 11:00 - 12:00
  
Prerequisites 1900100 Computer Skills
Time and Room
bulletSection 1: Sun, Tue, and Thu 4:00-5:000, CPE 001 (Eng. Manasrah)
bulletSection 2: Mon and Wed 9:30-11:00, CPE 001 (Dr. Abandah)
bulletSection 3: Mon and Wed 2:00-3:30, CPE 001 (Dr. Abandah)
bulletSection 4: Mon and Wed 3:30-5:00, CE 002 (Dr. Sarhan)
Textbook Logic and Computer Design Fundamentals, M. Morris Mano and Charles R. Kime (4th edition, 2008), Prentice Hall
Grading
Midterm Exam 30%
3 Homeworks and 2 Tests: 3 Marks for each homework, and 11 marks for the 2 tests. 20%
Final Exam 50%
   
Policies
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Attendance is required.

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All submitted work must be yours.

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Cheating will not be tolerated.

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Homeworks are due on exam or test dates
Tentative Outline
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Digital Systems and Numbering Systems

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Combinational Logic Circuits

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Combinational Logic Design

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Arithmetic Functions and HDLs

Midterm Exam

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Sequential Circuits

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Selected Design Topics

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Registers and Register Transfers

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Memory Basics

Final Exam

Special Dates
Sun 14 Sep 2008 Classes Begin
Wed 8 Oct 2008 Homework 1 Announcement
Wed 15 Oct 2008 Test 1 and Homework 1 Due
Wed 29 Oct 2008 Homework 2 Announcement
Wed 5 Nov 2008

Midterm Exam 5:00-6:00 pm

   Section 1 in Middle Auditorium

   Section 2 in ChE 101 and CHE 103

   Section 3 in EE 002 and ChE 002

   Section 4 in Small Auditorium

Homework 2 Due in class
Wed 3 Dec 2008 Homework 3 Announcement
Wed 17 Dec 2008 Test 2 and Homework 3 Due
Sun 11 Jan 2009 Last Lecture
Wed 14 Jun 2009 Final Exam 2:00-4:00 pm (This is the confirmed exam date)
Handouts Course Outline

Slides

  1. Introduction and Numbering Systems
  2. Combinational Logic Circuits - Part 1
  3. Combinational Logic Circuits - Part 2
  4. Combinational Logic Circuits - Part 3
  5. Combinational Logic Design - Part 1
  6. Combinational Logic Design - Part 2
  7. Arithmetic Functions
  8. Sequential Circuits - Part 1
  9. Sequential Circuits - Part 2
  10. Registers, Register Transfers, and Counters
  11. Programmable Implementation Technologies
  12. Memory Basics

Homeworks

  1. Homework 1: Due on Wed 15 Oct 2008, Solution
  2. Homework 2: Due on Wed 5 Nov 2008, Solution.
  3. Homework 3: Due on Wed 17 Dec 2008 in the class, submit handwritten answers, Solution.

Quizzes and Exams

  1. Solutions of quizzes given on Wed Oct 15, 2008 (Sections 2 and 3): Q1A, Q1B, Q1C, Q1D
  2. Solution of the midterm exam.
  3. Solutions of quizzes given on Wed Dec 16, 2008 (Sections 2 and 3): Q2A, Q2B, Q2C, Q2D
 

Grades for Section 1 (updated 1/1/2009)

Grades for Section 2 & 3 (updated 1/1/2009)

Grades for Section 4 (updated 1/1/2009)